library IEEE;
use IEEE.std_logic_1164.all;

entity adder is
	port(a, b, c : in std_logic;
		cout, sum : out std_logic);
end adder;

architecture structure of adder is
begin
	sum <= a xor b xor c;
	cout<= (c and (a xor b)) or (a and b);
end structure;

library IEEE;
use IEEE.std_logic_1164.all;

entity onebitalu is
	port (a, b, cin : in std_logic;
		op : in std_logic_vector(1 downto 0);
		result,CarryOut : out std_logic);
end onebitalu;

architecture structure of onebitalu is
	signal b1,AandB,AorB,AsumB,sub,cin1 : std_logic;

	component adder
		port (a,b,c : in std_logic;
			cout, sum : out std_logic);
	end component;
begin
	sub <= Op(1) and Op(0);
	cin1 <= cin or sub;
	b1 <= b xor sub;
	AandB <= a and b1;
	AorB <= a or b1;
	
	adder1 : adder
		port map(a, b1, cin1, CarryOut, AsumB);

	result <= (AandB and not Op(1) and not Op(0)) or	
			  (AorB and not Op(1) and Op(0)) or
			  (AsumB and Op(1) and not Op(0)) or 
			  (AsumB and Op(1) and Op(0));
end structure;

library IEEE;
use IEEE.std_logic_1164.all;

entity nBitAlu is
	port (a,b : in std_logic_vector(15 downto 0);
		result : out std_logic_vector(15 downto 0);
		Op : in std_logic_vector (1 downto 0);
		CarryOut, zero : out std_logic);
end nBitAlu;

architecture structure of nBitAlu is
	signal carryb : std_logic_vector(16 downto 0);

	component onebitalu
		port (a, b, cin : in std_logic;
			Op : in std_logic_vector(1 downto 0);
			result, CarryOut : out std_logic);
	end component;
	signal resulti : std_logic_vector(15 downto 0);
begin
	carryb(0) <= '0';
	CarryOut <= carryb(16);
	alu_generate:
	for i in 0 to 15 generate
		alu : onebitalu
			port map(a(i), b(i), carryb(i), Op, resulti(i), carryb(i+1));
	end generate;

	result <= resulti;

	with resulti select
		zero <= '1' when "0000000000000000",
			    '0' when others;
end structure; 		

library IEEE;
use IEEE.std_logic_1164.all;

package mips_package is
	component nBitAlu
		port (a,b : in std_logic_vector(15 downto 0);
			result : out std_logic_vector(15 downto 0);
			Op : in std_logic_vector (1 downto 0);
			CarryOut, zero : out std_logic);
	end component;
end mips_package;
	
